Formal Verif Hw Sw Systems
6:10pm–8:00pm
Pupin Laboratories 329
Morningside
Seat data provenance: Directory as of August 23, 2026 at 4:00 AM
Description
Lect: 2. Introduction to the theory and practice of formal methods for the design and analysis of correct (i.e. bug-free) concurrent and embedded hardware/software systems. Topics include temporal logics; model checking; deadlock and liveness issues; fairness; satisfiability (SAT) checkers; binary decision diagrams (BDDs); abstraction techniques; introduction to commercial formal verification tools. Industrial state-of-art, case studies and experiences: software analysis (C/C /Java), hardware verification (RTL).
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Course experience
n=2, 2023–2026
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n=1, 2023
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Where it meets
Flat map — motion reduced
Workload and grading
- Grading
- Not published
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- Credits
- 3 credits
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